The function of an electronic package is to protect sensitive electronic components, in particular integrated semiconductor circuits, from harsh environments without inhibiting the electrical performance. The package is used to electrically and mechanically attach the respective electronic component to an intended electronic device or apparatus.
One popular family of electronic packages is the so called Micro Leadframe Package (MLP) also known as Quad-Flat-No-Lead (QFN) or Dual-Flat-No-Lead (DFN). MLP is based upon a patterned and etched metal mounting commonly with a central pad, onto which at least one electronic component is mounted, connected with wire bonds to isolated package pins, and then encapsulated by a plastic sealing material. The sealing material is applied around the metal of the mounting and the electronic component with the wire bonds to form a hard, protective plastic body.
In the electronic packaging industry there is a permanent desire on the one hand to reduce size and cost and on the other hand to increase the integrated functionality. One proven route to increase functionality is to include several integrated circuits in the same MLP.
Modern assembly techniques allow semiconductor dies to be stacked or flip mounted (i.e. mounted in an inverted orientation) known as “flip-chip” mounting. Thereby, the final package size can be kept small.
A further problem to be solved in the electronic packaging industry is the dissipation of unwanted thermal energy, which is produced by the packaged electronic component during normal operation. Therefore, an intelligent thermal design is also important in order to allow the maintenance of electrical and mechanical stability of the packaged component.
Another problem to be solved is that many electronics products need to operate in an electrically noisy environment. Therefore, measures for protecting a sensitive integrated circuit within the package from unwanted electrical interference in important in many applications.
EP 2 469 592 A1 discloses with FIG. 4 an integrated circuit chip package device comprising (a) a package base 30 with a cavity 40 formed therein, (b) a semiconductor die 20 being located in the cavity 40, and (c) a planar dielectric substrate 10 representing a cover for the package base 30 respectively for the semiconductor die 20. The semiconductor die 20 is electrically connected to conductor traces being formed at the surface of the dielectric substrate 10 by means of flip chip balls 50. The semiconductor die 20 mechanically and thermally connected to a center die pad 31 on the surface of the package base 30 by means of an adhesive layer 25.